Deskew circuit for differential signal
US11489516B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2021 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Nov 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0278
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A deskew circuit for a differential signal is provided. A first common mode voltage generating circuit generates a first common mode voltage signal according to first and second differential input signals. A voltage buffer circuit is coupled to the first common mode voltage generating circuit and has an input impedance higher than a preset value, and buffers the first common mode voltage signal and the first and second differential input signals to generate a second common mode voltage signal, a third differential input signal, and a fourth differential input signal. A second common mode voltage generating circuit is coupled to the voltage buffer circuit and generates a third common mode voltage signal according to the third and fourth differential input signals. An output circuit generates a deskew output signal according to the third and fourth differential input signals and the second and third common mode voltage signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.