Analog phase locked loop
US11489532B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2021 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Apr 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog PLL comprising: a VCO configured to provide a PLL output signal; a phase detector (PD) configured to receive a feedback signal from the VCO and a reference signal and wherein the PD provides a PD signal to a low pass filter (LPF), the LPF configured to filter of the PD signal and provide the filtered signal as a tuning voltage for the VCO; and a tracking loop configured to receive the tuning voltage and comprising at least a tracking loop comparator configured to provide a comparator output voltage based on a difference between the tuning voltage and a target voltage, wherein an output of the tracking loop provides a tracking voltage based on the comparator output voltage and wherein the frequency of the PLL output voltage is based on the tuning voltage and the tracking voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.