Digital-to-analog conversion architecture and method
US11489534B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2021 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Oct 11, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/0836
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital-to-analog converter (DAC) architecture, comprising: a matrix DAC array comprising a plurality of cells arranged in a first dimension and a second dimension, each cell comprising a local decoder configured to transition the cell between at least two states; and decoding circuitry configured to: receive a digital input signal; and control the plurality of local decoders based on a received digital input signal, wherein each incremental change in the digital input signal results in a transition of a single cell of the plurality of cells such that the plurality of cells transition in sequence, the sequence of transitions of the plurality of cells defining a path through the DAC array; wherein when the path proceeds in the first dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time; and wherein when the path proceeds in the second dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.