Analog-to-digital conversion
US11489538B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2018 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Sep 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.