Bit-level mode retimer
US11489657B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2021 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Oct 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/242
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed are some examples of retimer circuitry, systems and methods. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal. Phase interpolator circuitry is coupled with the clock data recovery circuitry. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track data packets of the data component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.