Extended JTAG controller and method for functional reset using the extended JTAG controller
US11493553B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 22, 2018 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Sep 14, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318575
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An extended joint test action group based controller and a method of use allows easier testing of integrated circuits by reducing the power dissipation of an IC. The extended joint test action group (JTAG) controller tests internal storage elements that form digital units in an integrated circuit (IC) use a design for testing scan infrastructure on the IC, wherein the JTAG controller is extended by an overall reset generator for all digital units of the IC, and a finite state machine controls the overall reset generator. In reset mode the JTAG controller stops the at least one clock module in supplying the digital units that should be reset. It then sets all scan chains in test mode and switches the input multiplexers into reset mode; and then controls the number of shift clock cycles for shifting in the reset value to the flip-flops in the scan chain, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.