Lithography method using multi-scale simulation, semiconductor device manufacturing method and exposure equipment
US11493850B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2019 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Jan 7, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B2219/45028
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.