Erase block trimming for heterogenous flash memory storage devices
US11494109B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2019 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Feb 21, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a solid-state storage array having a plurality of solid-state storage devices and a storage controller coupled to the solid-state storage array, the storage controller including a processing device, the processing device to determine that a first allocation unit has a first portion occupying a first plurality of erase blocks and a second portion sharing a second erase block with a portion of a second allocation unit. The processing device is further to relocate data of the portion of the second allocation unit sharing the second erase block with the second portion of the first allocation unit to another erase block and in response to relocating the data of the portion of the second allocation unit, reclaim the first plurality of erase blocks and the second erase block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.