Memory device for performing in-memory processing
US11494121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2020 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Nov 16, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes: in-memory operation units to perform in-memory processing of an operation pipelined in multi-pipeline stages; memory banks assigned to the plurality of in-memory operation units such that a set of n memory banks is assigned to each of the in-memory operation units, each memory bank performing an access operation of data requested by each of the plurality of in-memory operation units while the pipelined operation is performed, wherein n is a natural number; and a memory die in which the in-memory operation units, the memory banks, and command pads configured to receive a command signal from an external source are arranged. Each set of the n memory banks includes a first memory bank having a first data transmission distance to the command pads and a second memory bank having a second data transmission distance to the command pads that is larger than the first data transmission distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.