Methods and devices for bypassing the internal cache of an advanced DRAM memory controller
US11494308B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Sep 6, 2017 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Apr 4, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A calculation system comprises a computing device having one or more instruction-controlled processing cores and a memory controller, the memory controller including a cache memory; and a memory circuit coupled to the memory controller via a data bus and an address bus, the memory circuit being adapted to have a first m-bit memory location accessible by a plurality of first addresses provided on the address bus, the calculation device being configured to select, in order to each memory operation accessing the first m-bit memory location, one address among the plurality first addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.