Delayed link compression scheme
US11494320B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2018 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Dec 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus, systems and methods for implementing delayed decompression schemes. As a burst of packets comprising compressed packets and uncompressed packets are received over an interconnect link, they are buffered in a receive buffer without decompression. Subsequently, the packets are forwarded from the receive buffer to a consumer such as processor core, with the compressed packets being decompressed prior to reaching the processor core. Under a first delayed decompression approach, packets are decompressed when they are read from the receive buffer in conjunction with forwarding the uncompressed packet (or uncompressed data contained therein) to the consumer. Under a second delayed decompression scheme, the packets are read from the receive buffer and forwarded to a decompressor using a first datapath width matching the width of the packets, decompressed, and then forwarded to the consumer using a second datapath width matching the width of the uncompressed data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.