Semiconductor device, method of generating layout diagram and system for same
US11494542B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2020 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Sep 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5226
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes: an active area in a transistor layer; contact-source/drain (CSD) conductors in the transistor layer; gate conductors in the transistor layer, and interleaved with the CSD conductors; VG structures in the transistor layer, and over the active area; and a first gate-signal-carrying (GSC) conductor in an M_1st layer that is over the transistor layer, and that is over the active area; and wherein long axes correspondingly of the active area and the first GSC conductor extend substantially in a first direction; and long axes correspondingly of the CSD conductors and the gate conductors extend substantially in a second direction, the second direction being substantially perpendicular to the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.