Memory unit for multi-bit convolutional neural network based computing-in-memory applications, memory array structure for multi-bit convolutional neural network based computing-in-memory applications and computing method
US11495287B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2019 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Mar 20, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory unit is controlled by a first word line and a second word line. The memory unit includes a memory cell and a transpose cell. The memory cell stores a weight. The memory cell is controlled by the first word line and includes a local bit line transmitting the weight. The transpose cell is connected to the memory cell and receives the weight via the local bit line. The transpose cell includes an input bit line, an input bit line bar, an output bit line and an output bit line bar. Each of the input bit line and the input bit line bar transmits a multi-bit input value, and the transpose cell is controlled by the second word line to generate a multi-bit output value on each of the output bit line and the output bit line bar according to the multi-bit input value and the weight.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.