Stacked semiconductor device and multiple chips used therein
US11495565B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 2019 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Dec 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/81052
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor device encompasses a mother-substrate, rectangular chips mounted on the mother-substrate, and bump-connecting mechanisms connecting the mother-substrate and the chips by a non-provisional joint-process with a height lower than the height of a provisional joint-process jointing the mother-substrate and the chips. The mother-substrate has unit elements arranged in each of unit-element areas assigned to a first lattice defined on a first main surface of the mother-substrate, the first main surface is divided into chip-mounting areas along a second lattice having a smaller number of meshes than the first lattice. The bump-connecting mechanisms are arranged along a third lattice corresponding to the arrangement of the unit elements, and transmit signals from the unit elements independently to each of the circuits merged in the chips. After the provisional joint-process, the bump-connecting mechanisms can be separated into substrate-side and chip-side connection-elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.