Display apparatus
US11495650B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2020 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Jan 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A display apparatus includes a thin film transistor facing a substrate with a buffer layer therebetween and including a semiconductor layer, a channel region, a source region, a drain region, and a gate electrode; a conductive pattern between the substrate and the semiconductor layer and connected to the semiconductor layer, the conductive pattern facing the semiconductor layer with the buffer layer therebetween; a contact hole in the buffer layer and exposing the conductive pattern to outside the buffer layer; and a display element which is electrically connected to the thin film transistor. The source region or the drain region extends through the contact hole in the buffer layer, to contact the conductive pattern and connect the semiconductor layer to the conductive pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.