Multi-chip packaging of silicon photonics
US11500153B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2020 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Nov 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B2006/1213
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A multi-chip package assembly includes a substrate, a first semiconductor chip attached to the substrate, and a second semiconductor chip attached to the substrate, such that a portion of the second semiconductor chip overhangs an edge of the substrate. A first v-groove array for receiving a plurality of optical fibers is present within the portion of the second semiconductor chip that overhangs the edge of the substrate. An optical fiber assembly including the plurality of optical fibers is positioned and secured within the first v-groove array of the second semiconductor chip. The optical fiber assembly includes a second v-groove array configured to align the plurality of optical fibers to the first v-groove array of the second semiconductor chip. An end of each of the plurality of optical fibers is exposed for optical coupling within an optical fiber connector located at a distal end of the optical fiber assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.