Mask layout correction method and a method for fabricating semiconductor devices using the same
US11500283B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2020 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | May 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0337
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Disclosed are mask layout correction methods and a method for fabricating semiconductor devices. The mask layout correction method comprises performing a first optical proximity correction on an initial pattern layout. The step of performing the first optical proximity correction includes providing a target pattern of the initial pattern layout with control points based on a first model, obtaining a predicted contour of the initial pattern layout by performing a simulation, and obtaining an error between the target pattern and the predicted contour from the control points. The control points include first control points on an edge of the target pattern and second control points in an inside of the target pattern. The step of obtaining the error includes acquiring first error values from the first control points, providing weights to the first error values, and acquiring second error values from the second control points.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.