True random number generator circuit
US11500616B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | Jul 29, 2020 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Jun 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/588
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprises a noisy bias voltage generator circuit, a random seed generator circuit, and a random series generator circuit. The noisy bias voltage generator circuit may be configured to generate a plurality of noisy bias voltages in response to a plurality of input voltage signals and a first bias current signal. The random seed generator circuit may be configured to generate a random seed in response to the plurality of noisy bias voltages and a second bias current signal. The random series generator circuit may be configured to generate a series of true random bits in response to the random seed and a clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.