Processor core debugging with processor virtualization
US11500748B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2021 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Jun 23, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/366
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device, such as a system on a chip (SoC), includes a plurality of processor cores, a broadcaster module, a plurality of decoder units, and an aggregator module. The broadcaster module broadcasts a debug request from a debugger device to one or more of the plurality of processor cores via a bus, the debug request including an address specifying a logical identifier associated with a target processor core of the plurality of processor cores. The decoder units, associated with the processor cores, forward the debug request to a debug module of the respective processor core in response to detecting a match. If no match is detected, the decoder units forward the debug request to a subsequent processor core via the bus. The aggregator module forward a response message to the debugger device, the response message originating from the target processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.