Method and apparatus with neural network operation
US11501166B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 24, 2020 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | May 13, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor-implemented neural network method includes: generating a bit vector based on whether each of a plurality of input activations within a neural network is 0; merging the bit vector into the input activations such that bit values within the neural network included in the bit vector are most significant bits (MSBs) of multi bit expressions of the input activations; merging the bit vector into weights such that the bit values included in the bit vector are MSBs of multi bit expressions of the weights; sorting the input activations and the weights based on bits corresponding to the MSBs; and implementing the neural network, including performing operations between the sorted input activations and the sorted weights.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.