Methods of manufacturing semiconductor device and semiconductor device
US11502044B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2021 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Jun 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a CMP stop layer is formed over the first ILD layer, a trench opening is formed by patterning the CMP stop layer and the first ILD layer, an underlying first process mark is formed by forming a first conductive layer in the trench opening, a lower dielectric layer is formed over the underlying first process mark, a middle dielectric layer is formed over the lower dielectric layer, an upper dielectric layer is formed over the middle dielectric layer, a planarization operation is performed on the upper, middle and lower dielectric layers so that a part of the middle dielectric layer remains over the underlying first process mark, and a second process mark by the lower dielectric layer is formed by removing the remaining part of the middle dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.