Resistive random access memory device and methods of fabrication

US11502254B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Nathan Strutt · Beaverton, US
• Albert Chen · Portland, US
• Oleg Golonzka · Beaverton, US

Key dates

• Filing date: Sep 28, 2018
• Grant date: Nov 15, 2022
• Expiry date: Mar 15, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8833

Abstract

A memory device structure includes a first electrode, a second electrode, a switching layer between the first electrode and the second electrode, where the switching layer is to transition between first and second resistive states at a voltage threshold. The memory device further includes an oxygen exchange layer between the switching layer and the second electrode, where the oxygen exchange layer includes a metal and a sidewall oxide in contact with a sidewall of the oxygen exchange layer. The sidewall oxide includes the metal of the oxygen exchange layer and oxygen, and has a lateral thickness that exceed a thickness of the switching layer.