Patent · US Active

Optimized low Ron flatness gate driver

US11502674B2 · kind B2 · utility

0Cited by

3References

19Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Thomas A. Schmidt · Weilmünster, DE
Vikas Suma Vinay · Dallas, US

Key dates

Filing date	Jun 23, 2021
Grant date	Nov 15, 2022
Priority date	—
Expiry date	Jun 23, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2017/6878
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An analog switch includes a first field effect transistor (FET) which has a first terminal coupled to an input voltage terminal, a second terminal coupled to a common source, and a control terminal coupled to a common gate. The switch includes a second FET which has a first terminal coupled to an output voltage terminal, a second terminal coupled to the common source, and a control terminal coupled to the common gate. The switch includes a switched current source which has an input coupled to a high voltage supply terminal and an output coupled to the common gate. The switch includes a clamp circuit which has a first terminal coupled to the common gate, a second terminal coupled to the common source, and a third terminal coupled to the low voltage supply terminal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.