Method and device for clock generation and synchronization for time interleaved networks
US11507129B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2021 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Oct 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/662
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-layer time-interleaving (TI) device and method of operation therefor. This device includes a plurality of TI layers configured to receive a plurality of input clock signals and to output a plurality of output clock signals, each of which can be configured to drive subsequent devices. The layers include at least a first and second layer including a fine-grain propagation device and a barrel-shifting propagation device configured to retime the plurality of input clock signals to produce divided output clock signals. The device can include additional barrel-shifting propagation devices to time interleave an initial two layers to produce one or more additional layers. Using negative phase stepping, the plurality of output clock signals is produced with optimal timing margin and synchronized on a single clock edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.