Systems and methods for providing high-performance access to shared computer memory via different interconnect fabrics
US11507285B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2022 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Feb 16, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a controller for a disaggregated memory device. The controller may receive a request to allocate memory of a specific size from the disaggregated memory device to a computing device, and may generate a memory block device in the specific size from a memory pool formed from physical memory modules configured on the disaggregated memory device. The controller may expose the memory block device to the computing device as a Non-Volatile Memory Express (“NVMe”) target device, and may control access to the memory block device by converting NVMe access requests in a first format from the computing device to access requests in a different second format supported by the memory block device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.