Identifying non-correctable errors using error pattern analysis
US11507454B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 26, 2020 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Oct 26, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described for identifying patterns of memory cells in a memory array that are predictive of non-correctable errors (“corruption patterns”). The techniques described herein identify patterns of cell errors that are likely to generate errors that cannot be corrected by an error correction code (ECC). The identification of non-correctable cells is accomplished by identifying a pattern of cell errors storing bit values that deviate from corresponding expected values. The pattern of these memory cells and various combinations of the cells in the pattern are compared to patterns of cells that are known to be correctable using ECC. If the error pattern or one or more of the combinations of erroneous cells in the pattern are not associated with patterns that are correctable via ECC, the error pattern is identified as predictive of a likely uncorrectable error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.