High breaking capacity chip fuse
US11508542B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2021 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Nov 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01H2085/0414
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A high breaking capacity chip fuse including a bottom insulative layer, a first intermediate insulative layer, a second intermediate insulative layer, and a top insulative layer disposed in a stacked arrangement in the aforementioned order, a fusible element disposed between the first and second intermediate insulative layers and extending between electrically conductive first and second terminals at opposing longitudinal ends of the bottom insulative layer, the first intermediate insulative layer, the second intermediate insulative layer, and the top insulative layer, wherein the first and second intermediate insulative layers are formed of porous ceramic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.