Display backplane, method of manufacturing the same and display device using the same
US11508786B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2020 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Jul 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1201
Abstract
The disclosure provides a display backplane, a method of manufacturing the same, and a display device using the same. The display backplane includes a substrate; a thin film transistor structure layer disposed on one side of the substrate and including thin film transistors, a gate insulating layer, and an interlayer dielectric layer, where an etching rate of the interlayer dielectric layer carried out under an HF atmosphere condition is less than 2 Å/S; and photosensitive devices spaced apart from the thin film transistor structure layer and disposed on one side of the thin film transistor structure layer away from the substrate. The interlayer dielectric layer has a high compactness, and can effectively block H from entering the active layer of the thin film transistor to conductorize the active layer, thus guaranteeing good optical characteristics of the thin film transistor while carrying out optical compensation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.