High-speed flip flop circuit including delay circuit
US11509295B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2021 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Jun 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3562
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A flip flop includes a master latch and a slave latch. The master latch includes a delay circuit configured to receive a clock signal and generate a first internal signal, and is configured to generate an internal output signal by latching a data signal based on the first internal signal. The slave latch is configured to generate a final signal by latching the internal output signal. The delay circuit is further configured to generate the first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level and generate the first internal signal based on the data signal when the clock signal has a second logic level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.