Glitch power analysis and optimization engine
US11509303B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2020 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | May 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00346
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A switching activity report of simulated switching activities of a semiconductor circuit is accessed. A plurality of glitch bottleneck ratios corresponding to a plurality of pins in the semiconductor circuit are determined, comprising by: setting an initial bottleneck ratio on a leaf output pin; and backward traversing the semiconductor circuit to determine a plurality of glitch bottleneck ratios of pins in a fan-in cone of the leaf output pin.A plurality of total glitch powers associated with the plurality of pins is determined, a total glitch power of the plurality of total glitch powers being determined based on a glitch bottleneck ratio and a glitch power of a corresponding pin. One or more critical bottleneck pins among the plurality of pins are identified based on the plurality of total glitch powers. One or more gates associated with the one or more critical bottleneck pins are adjusted to reduce corresponding one or more total glitch powers of the one or more gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.