Concurrent compute and ECC for in-memory matrix vector operations
US11513893B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2020 |
| Grant date | Nov 29, 2022 |
| Priority date | — |
| Expiry date | Jan 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a compute circuit that preemptively performs a computation on a data word before receiving an indication of data errors from an error checking and correction (ECC) circuit. The ECC circuit reads the data word from a memory array and performs error detection and error correction on the data word. The compute circuit reads the data word and performs the computation on the data word to generate an output value, without waiting for the ECC circuit to check and correct the data word. In response to error detection in the data word by the ECC circuit, the compute circuit delays outputting the output value until correction of the output value in accordance with the error detection by the ECC circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.