Variable resistance memory devices
US11514954B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2021 |
| Grant date | Nov 29, 2022 |
| Priority date | — |
| Expiry date | Jun 1, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit memory device includes a plurality of row selection transistors and a dummy row selection transistor, on a substrate. A plurality of word lines and a plurality of dummy word lines are also provided on the substrate. A plurality of memory cells are provided, which are electrically connected to corresponding ones of the plurality of word lines. A plurality of dummy memory cells are provided, which are electrically connected to corresponding ones of the plurality of dummy word lines. A first wiring structure is provided, which electrically connects a first one of the plurality of word lines to a first one of the plurality of row selection transistors, and a second wiring structure is provided, which electrically connects the plurality of dummy word lines together and to the dummy row selection transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.