SOT MRAM cell and array comprising a plurality of SOT MRAM cells
US11514963B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2020 |
| Grant date | Nov 29, 2022 |
| Priority date | — |
| Expiry date | Dec 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SOT-MRAM cell, comprising at least one magnetic tunnel junction (MTJ) comprising a tunnel barrier layer between a pinned ferromagnetic layer and a free ferromagnetic layer; a SOT line, extending substantially parallel to the plane of the layers and contacting a first end of said at least one MTJ; at least a first source line connected to one end of the SOT line; at least a first bit line and a second bit line, wherein the SOT-MRAM cell comprises one MTJ, each bit line being connected to the other end of the MTJ; or wherein the SOT-MRAM cell comprises two MTJs, each MTJ being connected to one of the first bit line and second bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.