Memory controller, and memory system including the same and method thereof
US11514971B2 · kind B2 · utility
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6References
20Claims
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Key dates
| Filing date | Apr 30, 2021 |
| Grant date | Nov 29, 2022 |
| Priority date | — |
| Expiry date | May 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes a clock signal generator generating a clock signal; a first data receiving circuit receiving a serial signal having a plurality of logic values from a memory, using the serial signal to compensate for a phase error of the clock signal, and generating a phase-compensated clock signal as a first clock signal; and at least one second data receiving circuit receiving data from the memory, receiving the first clock signal from the first data receiving circuit, and using the first clock signal to recover the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.