Semiconductor package and method of fabricating the same
US11515262B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2020 |
| Grant date | Nov 29, 2022 |
| Priority date | — |
| Expiry date | Jan 29, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first substrate including a first recess formed in a top surface of the first substrate, a first semiconductor chip disposed in the first recess and mounted on the first substrate, an interposer substrate disposed on the first semiconductor chip and including a second recess formed in a bottom surface of the interposer substrate, an adhesive layer disposed in the second recess and in contact with a top surface of the first semiconductor chip, a plurality of connection terminals spaced apart from the first recess and connecting the first substrate to the interposer substrate, and a molding layer disposed between the first substrate and the interposer substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.