Communication interface structure between processing die and memory die
US11515278B2 · kind B2 · utility
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Key dates
| Filing date | Feb 25, 2021 |
| Grant date | Nov 29, 2022 |
| Priority date | — |
| Expiry date | Apr 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A communication interface structure for connection between dies is provided, including a memory die, processing dies and interconnection routings. The memory die includes a first interface edge, wherein the first interface edge is split into a plurality of interface groups. Each of the processing dies includes a second interface edge. Interconnection routings respectively connect the second interface edges of the processing dies to the interface groups of the memory die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.