Stacked vertically isolated MOSFET structure and method of forming the same

US11515334B2 · kind B2 · utility

Assignee

• National Taiwan University · TW

Inventors

• Yu-Shiang Huang · Taichung, TW
• Hung-Yu Yeh · Taichung, TW
• Wen-Hung Huang
• Chee-Wee Liu · Taipei, TW

Key dates

• Filing date: Aug 14, 2020
• Grant date: Nov 29, 2022
• Expiry date: Jun 1, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/797

Abstract

A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed. In an embodiment, the method may include depositing a first buffer layer over a substrate; depositing a first channel layer over the first buffer layer; depositing a second buffer layer over the first channel layer; depositing a second channel layer over the second buffer layer; depositing a third buffer layer over the second channel layer; etching the first buffer layer, the first channel layer, the second buffer layer, the second channel layer, and the third buffer layer to form a fin structure; etching the first buffer layer, the second buffer layer, and the third buffer layer to form a first plurality of openings; forming a first gate stack in the first opening disposed in the first buffer layer, a second gate stack in the first opening disposed in the second buffer layer, and a third gate stack in the first opening disposed in the third buffer layer; and replacing the second buffer layer and a portion of the second gate stack with an isolation structure.