Thin poly field plate design
US11515398B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2020 |
| Grant date | Nov 29, 2022 |
| Priority date | — |
| Expiry date | Aug 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
Abstract
The present disclosure relates to a transistor device having source and drain regions within a substrate. A gate electrode is between the source and drain regions. A spacer has a lower lateral portion along an upper surface of the substrate between the gate electrode and the drain region, a vertical portion extending along a sidewall of the gate electrode, and an upper lateral portion extending from the vertical portion to an outermost sidewall directly over the gate electrode. A field plate is disposed along an upper surface and a sidewall of the spacer and is separated from the gate electrode and the substrate by the spacer. A first ILD layer overlies the substrate, the gate electrode, and the field plate. A first conductive contact has opposing outermost sidewalls intersecting a first horizontally extending surface of the field plate between the gate electrode and the drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.