Patent · US Active

Semiconductor structure and fabrication method thereof

US11515400B2 · kind B2 · utility

0Cited by
1References
17Claims
0Family size

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Key dates

Filing dateSep 1, 2020
Grant dateNov 29, 2022
Priority date
Expiry dateSep 1, 2040

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/691
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a substrate; forming a dummy gate structure including a dummy gate dielectric layer, an initial dummy gate electrode layer, and a first sidewall spacer; forming an isolation layer having a surface lower than or coplanar with the dummy gate structure; forming a dummy gate electrode layer having a surface lower than the isolation layer, and forming a first opening to expose a portion of the first sidewall spacer; forming a modified sidewall spacer from the exposed first sidewall spacer; forming a second opening by removing the dummy gate electrode layer; forming a third opening by removing the dummy gate dielectric layer and the modified sidewall spacer, where top of the third opening has a size larger than bottom of the third opening; and forming a gate structure in the third opening.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.