Silicon rich nitride layer between a plurality of semiconductor layers
US11515411B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 16, 2021 |
| Grant date | Nov 29, 2022 |
| Priority date | — |
| Expiry date | Apr 17, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.