Semiconductor device
US11515421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2021 |
| Grant date | Nov 29, 2022 |
| Priority date | — |
| Expiry date | Mar 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.