Extended JTAG controller and method for functional debugging using the extended JTAG controller
US11519961B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 22, 2018 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Aug 22, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318597
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The invention discloses an extended joint test action group based controller and a method for functional debugging using the extended joint test action group based controller. The object of the invention to lower the power dissipation (dynamic and leakage) but providing the same functionality of the testing and debugging procedures at the same time will be solved by an extended joint test action group (JTAG) controller for testing flip-flops of a register of an integrated circuit (IC) using a design for testing scan infrastructure on the IC which comprises at least one scan chain, wherein an external debugger is connected to the design for testing scan infrastructure via the JTAG controller which is extended by a debug controller, whereas a feedback loop is formed from an output of the scan chain to an input multiplexer of the scan chain which is activated according to the extended JTAG controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.