Systems and methods for intercycle gap refresh and backpressure management
US11520531B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2020 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Dec 31, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/348
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system may include a synchronization device and an emulation chip including a processor and a memory. The processor may evaluate, during a first cycle, at least one of a set of one or more execution instructions in the memory or evaluation primitives configured to emulate a circuit, and evaluate, during a second cycle, at least one of the set of one or more execution instructions or a set of configured logic primitives. The synchronization device may interpose a gap period interposed between the first cycle and the second cycle such that during the gap period, the processor does not evaluate one or more instructions from the set of one or more execution instructions or re-evaluate primitives. The synchronization device may cause, during the first gap period, the emulation chip to perform refreshes on the memory of the emulation chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.