Selective boot sequence controller for resilient storage memory
US11520596B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2020 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Nov 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device for booting a host computing device includes a first storage memory region having a first storage memory controller, a second storage memory region having a second storage memory controller, and a resilient boot controller. The resilient boot controller is configured to store boot code in the first storage memory region, prevent write access by the host computing device through the first storage memory controller to the first storage memory region, detect a reset of the host computing device through the input/output interface, copy at least a portion of the boot code from the first storage memory region to the second storage memory region, responsive to detection of the reset of the host computing device, and enable read access of the copied boot code by the host computing device through the second storage memory controller of the second storage memory region, responsive to the copy operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.