System and method for controlling faults in system-on-chip
US11520653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2020 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Feb 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system-on-chip (SoC) is disclosed. The SoC includes a fault controlling circuit and processing circuits. The fault controlling circuit is configured to receive fault events generated by fault sources of the SoC and categorize the fault events based on a priority associated with each fault event. The fault controlling circuit is further configured to identify corresponding fault reactions for the categorized fault events and generate a set of recovery signals based on the identified fault reactions. The processing circuits are configured to receive the fault events, and further configured to receive the set of recovery signals to recover from the fault events. The fault controlling circuit thus acts as a central control system for controlling faults in the SoC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.