Storage devices hiding parity swapping behavior
US11520660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2021 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Jun 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. By restricting the host to have a minimum write size, the data transfer speed to RAM2, RAM1, and the storage unit can be optimized. A temporary buffer is utilized within the RAM1 to update parity data for the corresponding commands. The parity data is updated in the RAM1 and written to the RAM2 in the corresponding zone. The parity data may be copied from the RAM2 to the RAM1 to update the parity data in the temporary buffer when commands are received to write data to corresponding zones. As the parity data is updated, the corresponding command is simultaneously written to the corresponding zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.