Scheduling of data refresh in a memory based on decoding latencies
US11520661B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2021 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Jul 12, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a memory and one or more processors. The memory includes multiple memory blocks. The one or more processors are configured to read at least part of data stored in a group of one or more memory blocks, the data including multiple code words of an Error Correction Code (ECC) that is decodable using one or more processing elements selected from among multiple predefined processing elements. The one or more processor are further configured to decode one or more of the code words, and identify one or more of the predefined processing elements that actually participated in decoding the respective code words, and, based on cost-values associated with the identified processing elements, the cost-values are indicative of processing latencies respectively incurred by the identified processing elements, to make a decision of whether or not to refresh the one or more memory blocks in the group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.