Digital interface circuit for sequencing analog-to-digital converter
US11520721B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 20, 2020 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Nov 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.