Automated assisted circuit validation
US11520966B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 8, 2021 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Jul 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method comprising categorizing nodes of a fabricated circuit as being priority nodes and nodes as being inferior nodes; evaluating a first priority node by automatically designating for verification the first priority node, and ascertaining whether a measured signal from the first priority node meets a pass-fail criterion for the first priority node; evaluating, when the measured signal from the first priority node meets the pass-fail criterion, a second priority node by automatically designating for verification the second priority node, and ascertaining whether a measured signal from the second priority node meets a pass-fail criterion for the second priority node; and evaluating, when the measured signal from the first priority node does not meet the pass-fail criterion, a first inferior node, by automatically designating for verification the first inferior node, and ascertaining whether a measured signal from the first inferior node meets a pass-fail criterion for the first inferior node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.