Method and device for latency reduction of an image processing pipeline
US11521291B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2021 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Jul 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/44218
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In some implementations, a method of reducing latency associated with an image read-out operation is performed at a device including one or more processors, non-transitory memory, an image processing architecture, and an image capture device. The method includes: obtaining first image data corresponding to a physical environment; reading a first slice of the first image data into an input buffer; performing processing operations on the first slice of the first image data to obtain a first portion of second image data; reading a second slice of the first image data into the input buffer; performing the image processing operations on the second slice of the first image data to obtain a second portion of the second image data; and generating an image frame of the physical environment based at least in part on the first and second portions of the second image data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.